1. Field of the Invention
The present invention relates to a display apparatus and a method for a pixel array to display an image. More particularly, the present invention relates to a display apparatus with a system-on-glass (SOG) and a method for a pixel array to display an image.
2. Descriptions of the Related Art
Over recent years, flat panel displays have gradually replaced conventional cathode ray tube (CRT) displays due to the rapid pace of developing the flat panel displays. Flat panel displays currently available primarily fall into the following categories: organic light-emitting diode displays (OLEDs), plasma display panels (PDPs), liquid crystal displays (LCDs), and field emission displays (FEDs). Among these flat panel displays, the LCDs have become the main product in the display market because of their advantages, such as low power consumption, a light weight, thin profile, and high definition.
LCDs typically adopt external drive circuits, control circuits and data circuits to connect to an array of the LCD. LCD manufacturers usually integrate these drive circuits, control circuits and data circuits into a single printed circuit board (PCB). Flexible wires are configured to connect the PCB to the array. To further compress the volume of an LCD, manufacturers have developed a manufacturing technology known as the SOG, i.e., the drive circuits and control circuits are formed directly on the array instead of being separately formed. This technology may save space and lower the cost of the drive circuits and control circuits that would otherwise be independently formed.
However, the driver circuits on array are inferior to the external drive circuits with regards to their driving capability. As a result, gate driver cannot adequately be charged, mostly resulting in degraded driving pixels on the array. In view of this, manufacturers have developed particular driving methods to prevent of the inadequate driving capability that occurs in the driving circuits of an LCD adopting the SOG technology.
As shown in FIG. 1A, an LCD 1 using an SOG generally comprises a drive integrated circuit (IC) 11, a first gate circuit 13 of gate driver on array (GOA), a second gate circuit 15, a plurality of scan lines (for simplicity, only 101b, 101g, 101r, 103b, 103g, 103r, 105b, 105g, 105r are denoted in FIG. 1A), and a plurality of pixels. The drive IC 11 is configured to send a first clock signal 10 and a first inverted clock signal 14 to the first gate circuit 13, and also to send a second clock signal 12 and a second inverted clock signal 16 to the second gate circuit 15. The first gate circuit 13 and the second gate circuit 15 may control the ON and OFF status of the pixels connected with each of the scan lines 101b, 101g, 101r, 103b, 103g, 103r, 105b, 105g, 105r according to the first clock signal 10, the first inverted clock signal 14, the second clock signal 12 and the second inverted clock signal 16 respectively. By sending the image data DATA from the drive IC 11 to the pixels and controlling the ON and OFF status of the corresponding pixels, an image can be displayed on the LCD 1. When the first gate circuit 13 turns on the scan line 101b and writes data DATA, the second gate circuit 15 turns on the scan line 101g to pre-charge the pixels on the scan line 101g before writing the data DATA to enhance the driving capability of the LCD 1. However, this method of improving the driving capability by pre-charging the pixels will result in two scan lines that will be turned on during the same time period. This may cause the image data DATA sent by the drive IC 11 to be written into the pixels on two adjacent scan lines, thus leading to errors in data writing and the erroneous display of the image on the LCD 1.
In the following description, various driving methods of pre-charging the pixels on the scan lines will be described respectively. FIG. 1B is a schematic clock diagram of individual scan lines that adopt the dot inversion driving method. When the LCD 1 is displaying the Nth frame of an image, the first gate circuit 13 turns on the scan line 101b during a period 100p of the first clock signal 10 to pre-charge the pixels on the scan line 101b before the data on the scan line 101b is outputted to pixels thereon. Subsequently, the data on the scan line 101b is outputted by the drive IC 11 to the pixels on the scan line 101b during a period 100 of the first clock signal 10. Meanwhile, the second gate circuit 15 turns on the scan line 101g during a period 102p of the second clock signal 12 to pre-charge the pixels on the scan line 101g. Then, the data on the scan line 101g is outputted by the drive IC 11 to the pixels on the scan line 101g during a period 102 of the second clock signal 12. Meanwhile, the first gate circuit 13 turns on the scan line 101r during a period 104p of the first inverted clock signal 14 to pre-charge the pixels on the scan line 101r. Next, the data on the scan line 101r is outputted by the drive IC 11 to the pixels on the scan line 101r during a period 104 of the first inverted clock signal 14. Similarly, when the data on the scan line 101r is being outputted to the pixels on the scan line 101r during the period 104 of the first inverted clock signal 14, the second gate circuit 15 turns on the scan line 103b during a period 106p of the second inverted clock signal 16 to pre-charge the pixels on the scan line 103b. The data on the scan line 103b is outputted by the drive IC 11 to the pixels on the scan line 103b during a period 106 of the second inverted clock signal 16. According to the first clock signal 10, the first inverted clock signal 14, the second clock signal 12 and the second inverted clock signal 16, the image data DATA is written by the drive IC 11 into all the pixels on the array.
With the dot inversion driving method, the data of two adjacent pixels have different polarities (POLs). That is, the data of pixels on the scan line 101b and the data of pixels on the scan line 101g have opposite polarities. The data of pixels on the scan line 101g and data of pixels on the scan line 101r have opposite polarities, too. For example, if the pixel data on the scan lines 101b, 101r and 103g have a positive polarity, then the data of pixels on the scan lines 101g, 103b and 103r have a negative polarity. Consequently, when the pixels on the scan line 101g are being pre-charged during the period 102p of the second clock signal 12, the data that will be written into the pixels on the scan lines 101b will also be written into the pixels on the scan line 101g simultaneously. However, opposite data polarities of the adjacent pixels lead to the significant difference between the image data thereof. More specifically, as the scan line 101g is being pre-charged, there is a significant difference between the data written into the pixels on the scan line 101b and the data that should be written into the pixels on the scan line 101g, which will adversely impact the image displaying quality of the LCD 1. Likewise, when the pixels on the scan line 101r are being pre-charged during the period 104p of the first inverted clock signal 14, data that will be written into the pixels on the scan lines 101g will also be written into the pixels on the scan line 101r simultaneously. When the pixels on the scan line 103b are pre-charged during the period 106p of the second inverted clock signal 16, data that will be written into the pixels on the scan lines 101r will also be written into the pixels on the scan line 103b simultaneously. Hence, whenever a scan line is pre-charged, opposite polarities will occur between the data written into the pixels on the scan line and the data that ought to be ultimate written therein. As a result, there are errors in writing the data of the three colors in each frame period.
To overcome this problem, there are many different driving methods that have been proposed in the prior art. For instance, FIG. 1C is a schematic clock diagram of individual scan lines that have adopted a one-three line dot inversion driving method. As shown in FIG. 1C, the drive IC 11 outputs one pixel data of a positive polarity and then outputs three pixel data of a negative polarity in succession. To be more specific, the data of pixels on the scan lines 101b, 103g have a positive polarity, while the data of the pixels on the scan lines 101g, 101r, 103b, 103r have a negative polarity. It can be seen from FIG. 1C that when the pixels on the scan line 101g are pre-charged during a period 102p of the second clock signal 12, pixels on the scan line 103g are pre-charged during a period 108p of the first clock signal 10, while the pixels on the scan line 103r are pre-charged during a period 110p of the second clock signal 12. During this process, opposite polarities will occur between the data written into the pixels on the scan lines during the respective pre-charging processes and the data ought to be ultimate written therein.
FIG. 1D is a schematic clock diagram of individual scan lines that have adopted a two-three line dot inversion driving method. As shown in FIG. 1D, the drive IC 11 outputs two pixel data of a positive polarity and then outputs three pixel data of a negative polarity in succession. To be more specific, the pixel data of the scan lines 101b, 101g, 103r have a positive polarity, while the pixel data on the scan lines 101r, 103b, 103g have a negative polarity. Hence, with the two-three line dot inversion driving method, the opposite polarities that occur between the data that is written into the pixels on a scan line during the pre-charging process and the data that ought to be written therein occurs only when the pixels on the scan line 101r are being pre-charged during a period 104p of the first inverted clock signal 14 and when the pixels on the scan line 103r are being pre-charged during a period 101p of the second clock signal 12.
FIG. 1E is a schematic clock diagram illustrating the individual scan lines that have adopted a three-three line dot inversion driving method. As shown in FIG. 1E, the drive IC 11 outputs the three pixel data of a positive polarity and then outputs the three pixel data of a negative polarity in succession. To be more specific, the data of the pixels on the scan lines 101b, 101g, 101r have a positive polarity, while the data of pixels on the scan lines 103b, 103g, 103r have a negative polarity. Hence, with the three-three line dot inversion driving method, the opposite polarities between the data written into the pixels on a scan line during the pre-charging process and the data ought to be written therein occurs only when the pixels on the scan line 103b are being pre-charged during a period 106p of the second inverted clock signal 16.
Although the dot inversion driving methods described above may enhance the driving capability of an LCD that adopts a GOA technology, when the drive IC 11 sends image data DATA to the pixels. However, they all lead to an erroneous polarity in writing the data of a particular color, thus causing an adverse impact on the quality of an image displayed by the LCD 1.
In view of this, it is highly desirable in the art to provide an LCD with an SOG that can prevent erroneous polarities from occurring between the pixels of the LCD when the image data is being written, thereby improving the quality of an image displayed by the LCD.